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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2011.2
- 수록면
- 46 - 51 (6page)
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초록· 키워드
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TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.
목차
Abstract
1. 서론
2. 해석 조건
3. 해석 결과 및 고찰
5. 결론
후기
참고문헌
참고문헌 (7)
참고문헌 신청
2. [학술대회논문] - T. Jiang / 2008 / 3D Integration-Present and Future / 2008 10th Electronics Packaging Technology Conference : 373 ~ 378
3. [학술대회논문] - N. Tanaka / 2002 / Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module / 2002 Electronic Components and Technology Conference : 473 ~ 479
4. [학술지(정기간행물)] - J. Zhang / 2006 / Modeling Thermal Stresses in 3-D IC Interwafer Interconnects / IEEE Transactions on Semiconductor Manufacturing 19 (4) : 437 ~ 448
5. [학술대회논문] - M.C. Hsieh / 2008 / Thermo-mechanical Simulations For 4-Layer Stacked IC Packages / EuroSimE Conf : 1 ~ 7
6. [학술대회논문] - N. Khan / 2008 / Development of 3D silicon module with TSV for system in packaging / Electronic Components and Technology Conference : 550 ~ 555
3. [학술대회논문] - N. Tanaka / 2002 / Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module / 2002 Electronic Components and Technology Conference : 473 ~ 479
4. [학술지(정기간행물)] - J. Zhang / 2006 / Modeling Thermal Stresses in 3-D IC Interwafer Interconnects / IEEE Transactions on Semiconductor Manufacturing 19 (4) : 437 ~ 448
5. [학술대회논문] - M.C. Hsieh / 2008 / Thermo-mechanical Simulations For 4-Layer Stacked IC Packages / EuroSimE Conf : 1 ~ 7
6. [학술대회논문] - N. Khan / 2008 / Development of 3D silicon module with TSV for system in packaging / Electronic Components and Technology Conference : 550 ~ 555
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UCI(KEPA) : I410-ECN-0101-2012-581-004322673