A low-jitter multi-phase All Digital Phase Locked Loops for 5Gbps SerDes Applications

Seung-Hoon Jung ,  Yun-Jeong Kim ,  Kwang-Jin Lee 외 5명

대한전자공학회 ISOCC

2006 .10

A JITTER FREE ALL DIGITAL PHASE LOCKED LOOP

Maya Su ,  esh ,  Samiha Mou 외 1명

ICVC : International Conference on VLSI and CAD

1995 .01

A low-jitter multi-phase ADPLL for 3Gbps SerDes Transceivers in 0.18um CMOS

Seung-Hoon Jung ,  Kwang-Jin Lee ,  Yun-Jeong Kim 외 5명

ICEIC : International Conference on Electronics, Informations and Communications

2006 .06

A High-speed SerDes Transceiver for Wireless Proximity Communication

Jongsun Kim ,  Jintae Kim

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2018 .02

Digital Phase Locked Loop에 관한 연구 ( A Study on the Digital phase Locked Loop )

양형규 ,  원동호

대한전자공학회 학술대회

1984 .01

Digital Phase Locked Loop에 관한 연구

양형규 ,  원동호

대한전자공학회 학술대회

1984 .11

3.125Gbps Multi-Channel SerDes Based on Digital Clock & Data Recovery

Bong-Joon Lee

대한전자공학회 워크샵

2004 .08

A Low Jitter Phase-Locked Loop based on a Charge Pump Current Controller

Chel Hu ,  YoungShig Choi

대한전자공학회 ISOCC

2004 .10

A Fast Lock and Low Jitter Phase Locked Loop with Locking Status Indicator

Sanghwa Yoon ,  Youngshig Choi ,  Hyekhwan Choi 외 1명

대한전자공학회 ISOCC

2004 .10

An 1.25 & 2.5-Gbps Dual Mode SERDES for PON System

Beom-seok Shin ,  Seong-Seop Lee ,  Jung-Yong Lee 외 2명

대한전자공학회 ISOCC

2005 .10

Analysis and Optimization of Phase Noise of 2 ㎓ All-Digital Phase-Locked Loop

Hee-Jin Yang ,  Deog-Kyoon Jeong

대한전자공학회 학술대회

2020 .08

1000BASE-X를 위한 SERDES의 설계

안기중 ,  정덕균

전자공학회지

2000 .10

Dual-Digital Phase-Locked Loop에 과한 연구 ( A Study on the Dual Digital Phase Locked Loop )

김수일 ,  이상범 ,  성상기 외 2명

한국통신학회 학술대회논문집

1987 .01

Digital Phase-Locked Loops의 위상 포착 과정에 관한 연구 ( Acquisition Behavior of a Class of Digital Phase-Locked Loops )

안종구 ,  은종관

전자공학회지

1982 .05

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Changchun Zhang ,  Ming Li ,  Zhigong Wang 외 5명

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2013 .08

A 0.18um CMOS Phase Locked Loop for Fast Locking Time for 10Gbps Optical Receiver

Ju-Pyo Hong ,  Kwang-Il Oh ,  Lee-Sup Kim

대한전자공학회 ISOCC

2006 .10

Design of a Low Jitter Phase Locked Loop for DVD RW

Sanghoon Hwang ,  Minkyu Song

대한전자공학회 ISOCC

2004 .10

New charge pump with perfect current matching characteristics for low-jitter PLL applications

Sun-Sik Pa ,  k ,  Na-Yeong Lee 외 3명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2015 .06

MATHEMATICAL PHASE NOISE MODEL FOR A PHASE-LOCKED-LOOP

Sethapong Limkumne ,  d ,  Duang 외 2명

제어로봇시스템학회 국제학술대회 논문집

2005 .06