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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.3
- 발행연도
- 2013.6
- 수록면
- 224 - 236 (13page)
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This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. SIMULATION AND CALIBRATION
Ⅲ. DC PERFORMANCE COMPARISON
Ⅳ. DYNAMIC PERFORMANCE COMPARISON
Ⅴ. CIRCUIT LEVEL PERFORMANCE COMPARISON
Ⅵ. CONCLUSIONS
REFERENCES
참고문헌 (36)
참고문헌 신청
1. [학술대회논문] - Th. Nirschl / 2004 / The tunneling field effect transistor (TFET) as an add-on for ultra-lowvoltage analog and digital processes / IEDM Tech. Dig. : 195 ~ 198
2. [학술지(정기간행물)] - E. H. Toh / 2007 / Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction / Appl. Phys. Lett. 91 (24) : 243505 ~
3. [학술지(정기간행물)] - W. Y. Choi / 2007 / Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec / IEEE Electron Device Lett. 28 (8) : 743 ~ 745
4. [학술대회논문] - F. Mayer / 2008 / Impact of SOI, Si1−xGexOI and GeOI substrates on CMOS compatible tunnel FET performance / IEDM Tech. Dig. : 1 ~ 5
5. [학술지(정기간행물)] - O. M. Nayfeh / 2008 / Design of tunneling field-effect transistors using strainedsilicon/ strained germanium type II staggered heterojunctions / IEEE Electron Device, Lett. 29 (9) : 1074 ~ 1077
2. [학술지(정기간행물)] - E. H. Toh / 2007 / Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction / Appl. Phys. Lett. 91 (24) : 243505 ~
3. [학술지(정기간행물)] - W. Y. Choi / 2007 / Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec / IEEE Electron Device Lett. 28 (8) : 743 ~ 745
4. [학술대회논문] - F. Mayer / 2008 / Impact of SOI, Si1−xGexOI and GeOI substrates on CMOS compatible tunnel FET performance / IEDM Tech. Dig. : 1 ~ 5
5. [학술지(정기간행물)] - O. M. Nayfeh / 2008 / Design of tunneling field-effect transistors using strainedsilicon/ strained germanium type II staggered heterojunctions / IEEE Electron Device, Lett. 29 (9) : 1074 ~ 1077
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