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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.2
- 발행연도
- 2014.4
- 수록면
- 184 - 188 (5page)
이용수
초록· 키워드
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There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability (V<SUB>WL,OPT</SUB> = 1.055 V) as well as to lower the minimum operating voltage for the read and write operations simultaneously (V<SUB>MIN,READ</SUB> = 0.58 V, VMIN,WRITE = 0.82 V for supply voltage (V<SUB>DD</SUB>) = 1.1 V).
목차
Abstract
I. INTRODUCTION
II. ASSISTIVE CIRCUIT
III. MEASUREMENT RESULT & DISCUSSION
IV. CONCLUSION
REFERENCES
참고문헌 (13)
참고문헌 신청
1. [학술대회논문] - C. Auth / 2012 / A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors / VLSI Symp. on Tech. Digest, USA : 131 ~ 132
2. [학술지(정기간행물)] - E. Seevinck / 1987 / Staticnoise margin analysis of MOS SRAM cells / IEEE Journal of Solid-State Circuits 22 (5) : 748 ~ 754
3. [학술대회논문] - A. Carlson / 2008 / Compensation of systematic variations through optimal biasing of SRAM wordlines / IEEE Custom Integrated Circuits Conference, USA : 411 ~ 413
4. [학술대회논문] - K. Nii / 2008 / A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment / VLSI Symp. on Circuit Digest, USA : 212 ~ 213
5. [학술대회논문] - Y. Fujimura / 2010 / A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149μm2 cell in 32nm high-k metal-gate CMOS / IEEE International Solid-State Circuits Conference, USA : 348 ~ 349
2. [학술지(정기간행물)] - E. Seevinck / 1987 / Staticnoise margin analysis of MOS SRAM cells / IEEE Journal of Solid-State Circuits 22 (5) : 748 ~ 754
3. [학술대회논문] - A. Carlson / 2008 / Compensation of systematic variations through optimal biasing of SRAM wordlines / IEEE Custom Integrated Circuits Conference, USA : 411 ~ 413
4. [학술대회논문] - K. Nii / 2008 / A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment / VLSI Symp. on Circuit Digest, USA : 212 ~ 213
5. [학술대회논문] - Y. Fujimura / 2010 / A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149μm2 cell in 32nm high-k metal-gate CMOS / IEEE International Solid-State Circuits Conference, USA : 348 ~ 349
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