지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.6
- 발행연도
- 2016.12
- 수록면
- 873 - 879 (7page)
이용수
초록· 키워드
오류제보하기
A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is 490 μA from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by 7.5 dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CIRCUIT DESIGN
Ⅲ. MEASUREMENT RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
[학술지(정기간행물)] - W. Rhee / 1999 / Design of high-performance CMOS charge pumps in phase-locked loops / IEEE Int. Symp. on Circuits and Systems 2 : 545 ~ 548
[학술지(정기간행물)] - N. Kamal / 2012 / An Accurate Analytical Spur Model for an Integer-N Phase-Locked Loop / Int. Conf. on Intelligent and Advanced Systems 2 : 659 ~ 664
[학술지(정기간행물)] - D. Mandal / 2015 / Prediction of reference spur in frequency synthesisers / IET Circuits, Devices & Systems 9 (2) : 131 ~ 139
[단행본] - K. Shu / 2005 / CMOS PLL Synthesizers / Springer
[학술지(정기간행물)] - P. Larsson / 1999 / A 2–1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability / IEEE J. of Solid-State Circuits 34 (12) : 1951 ~ 1960
[학술지(정기간행물)] - N. Kamal / 2012 / An Accurate Analytical Spur Model for an Integer-N Phase-Locked Loop / Int. Conf. on Intelligent and Advanced Systems 2 : 659 ~ 664
[학술지(정기간행물)] - D. Mandal / 2015 / Prediction of reference spur in frequency synthesisers / IET Circuits, Devices & Systems 9 (2) : 131 ~ 139
[단행본] - K. Shu / 2005 / CMOS PLL Synthesizers / Springer
[학술지(정기간행물)] - P. Larsson / 1999 / A 2–1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability / IEEE J. of Solid-State Circuits 34 (12) : 1951 ~ 1960
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UCI(KEPA) : I410-ECN-0101-2017-569-001935149