지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
초록· 키워드
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This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the rowto-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-μm CMOS process. A 160 × 120 pixel array with 4.4 μm pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.
목차
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참고문헌 (7)
참고문헌 신청
M. Amjad / 2018 / Wireless multimedia cognitive radio networks : A comprehensive survey / IEEE Commun. Surveys Tut. 20(2):1056~1103
H. Kim / 2021 / 11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors / Journal of Solid-State Circuits 56(7):2132~2141
H. J. Kim / 2016 / A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column Parallel SAR ADCs / Journal of Solid-State Circuits 51(10):2262~2273
H. J. Kim / 2017 / A Dual Imaging Speed-Enhanced CMOS Image Sensor for Real Time Edge Image Extraction / Journal of Solid-State Circuits 52(9):2488~2497
M. W. Seo / 2013 / A low noise wide dynamic range CMOS image sensor with low-noise transistors and 17b column-parallel ADCs / IEEE Sensors Journal 13(8):2992~2929
H. Kim / 2021 / 11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors / Journal of Solid-State Circuits 56(7):2132~2141
H. J. Kim / 2016 / A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column Parallel SAR ADCs / Journal of Solid-State Circuits 51(10):2262~2273
H. J. Kim / 2017 / A Dual Imaging Speed-Enhanced CMOS Image Sensor for Real Time Edge Image Extraction / Journal of Solid-State Circuits 52(9):2488~2497
M. W. Seo / 2013 / A low noise wide dynamic range CMOS image sensor with low-noise transistors and 17b column-parallel ADCs / IEEE Sensors Journal 13(8):2992~2929
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