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논문 기본 정보

자료유형
학술대회자료
저자정보
Hyeon-Sik Kim (Gachon University) Hyung-June Cho (Seoul National University) Seung-Ki Sul (Seoul National University)
저널정보
전력전자학회 ICPE(ISPE)논문집 ICPE 2023-ECCE Asia
발행연도
2023.5
수록면
2,205 - 2,211 (7page)

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This paper analyzes the possible zero clamping region of a three-level inverter to reduce switching loss and how to select positive, negative, and zero clamping in discontinuous PWM (DPWM). Based on these analyses, carrier-based minimum-loss DPWM (MLDPWM) is proposed for the three-level inverters within all ranges of power factor angle and high modulation index. Under consideration of not only positive and negative clamping but also zero clamping, the proposed method could increase the clamping region furthermore in the vicinity of a peak current at a lower power factor and higher modulation index. Thus, the switching loss can be minimized by reducing the number of switching near the peak current even under low power factor operation. The performance of the proposed method is compared with that of the conventional DPWM method in the aspect of switching loss function (SLF). Lastly, the effectiveness of the proposed method is verified by simulation and experimental results.

목차

Abstract
I. INTRODUCTION
II. ANALYSIS OF DPWM WITH THREE-LEVEL INVERTER
III. PROPOSED MINIMUM LOSS DISCONTINUOUS MODULATION SCHEME
IV. SIMULATION AND EXPERIMENTAL RESULTS
V. CONCLUSION
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