A New Burst Mode Clock and Data Recovery Circuit

Seung-Woo Lee ,  Chang-kyung Seong ,  Bhum-cheol Lee 외 1명

대한전자공학회 ISOCC

2007 .10

Design and Simulation of 622 Mb/s Burst Mode Clock Recovery Circuit Using Digital Logic Devices

Jae-Seung Hwang ,  Chul-Soo Pa ,  k 외 5명

한국통신학회 학술대회논문집

2001 .07

광대역 전디지털 클록 데이터 복원회로 설계

고귀한 ,  정기상 ,  김강직 외 1명

전기학회논문지

2012 .11

Wide Frequency Range를 위한 디지털 Phase Interpolator 설계

채주형 ,  홍기문 ,  김민오 외 2명

대한전자공학회 학술대회

2015 .06

A Wide Operation Frequency Range Frequency Clock Generator with Phase Interpolator

Wei-Bin Yang ,  Ho ,  ng-Yuan Shih 외 4명

대한전자공학회 ISOCC

2013 .11

Data and Clock Recovery with Digital Phase Alignment Scheme

Bhum Cheol Lee ,  Hee Young Jung ,  Kwon Chul Pa 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1997 .01

1Gb/s gated-oscillator burst mode CDR for half-rate clock recovery

Pyung-Su Han ,  Woo-Young Choi

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2004 .12

1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuit Using Gated-Oscillators

Pyung-Su Han ,  Woo-Young Choi

대한전자공학회 ISOCC

2005 .10

A Boundary Switching Problem of a Multi-bit Phase Interpolator

Soyeong Shin ,  Deog-kyoon Jeong

대한전자공학회 학술대회

2019 .06

이중 보간 방식을 이용한 CMOS 클록 데이터 복원회로

안희선 ,  이순재 ,  박원기 외 2명

대한전자공학회 학술대회

2009 .07

Variable Rate Clock and Data Recovery Circuit for Biomedical Application

HyungGu Pa ,  k ,  Hongjin Kim 외 1명

대한전자공학회 ISOCC

2012 .11

A 51.84 Mbit/s CMOS VLSI Digital Frame Phase Aligner

Sang-Hoon Lee ,  Jung-Hoon Ko ,  Chang-Sup Shim 외 1명

ICEIC : International Conference on Electronics, Informations and Communications

1995 .08

A 51 . 84 Mbit/s CMOS VLSI Digital Frame Phase Aligner

Sang Hoon Lee ,  Jung Hoon Ko ,  Chang Sup Shim 외 1명

ICEIC : International Conference on Electronics, Informations and Communications

1995 .01

A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits

Hyun Pa ,  k ,  Kang Wook Kim 외 2명

[ETRI] ETRI Journal

2008 .04

Wide-Tracking Range Clock and Data Recovery Circuit의 CPPSIM 모델링

김민오 ,  신우열 ,  홍기문 외 4명

대한전자공학회 학술대회

2009 .11

Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop

Jae Ho Song ,  Tae Whan Yoo ,  Jeong Hoon Ko 외 3명

[ETRI] ETRI Journal

1999 .06

Design of 2.5Gb/s non-PLL-type All-Digital Clock Recovery Circuit

Soojin Kim ,  Kyeongsoon Cho

대한전자공학회 ISOCC

2010 .11

A Referenceless Burst-Mode Clock and Data Recovery for Optical Communication Systems

Jae-Hun Jung ,  Kwang-Hyun Baek

대한전자공학회 ISOCC

2012 .11

A 1.25-Gb/s Clock and Data Recovery Circuit for Multichannel Application

Chang-kyung Seong ,  Seung-woo Lee ,  Woo-young Choi

대한전자공학회 ISOCC

2005 .10