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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Electrical Engineering and Information Science Journal of Electrical Engineering and Information Science Vol.2 No.3
- 발행연도
- 1997.6
- 수록면
- 14 - 21 (8page)
이용수
초록· 키워드
오류제보하기
In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the de1ay-optimized design in order to have the same defect-level for delay faults as the non~optimized design, while the system clock time is the same for both designs.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Delay Optimization of a Logic Network
Ⅲ. Manufacturing Yield and Delay Testing Quality in a Delay-Optimized Design
Ⅳ. Implications and Conclusions
Acknowledgement
References
저자소개
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