지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2016.3
- 수록면
- 532 - 541 (10page)
이용수
초록· 키워드
오류제보하기
A single-phase asymmetrical cascaded multilevel inverter is introduced with the goal of increasing power quality with the reduction of power in insulated-gate bipolar transistor (IGBT) switches. In the present work, the proposed inverter topology is analyzed and generalized with respect to different proposed algorithms for choosing different voltage source values. To prove the advantages of the proposed inverter, a case study involving a 17-level inverter is conducted. The simulation and experimental results with reduced THD are also presented and compared with the MATLAB/SIMULINK simulation results. Finally, the proposed topology is compared with different multilevel inverter topologies available in the literature in terms of the number of IGBT switches required with respect to the number of levels generated in the output of inverter topologies.
목차
Abstract
I. INTRODUCTION
II. PROPOSED TOPOLOGY
III. PROPOSED PARAMETER-GENERALIZED TOPOLOGY
IV. COMPARISON OF PROPOSED TOPOLOGY WITH CONVENTIONAL TOPOLOGIES
V. SIMULATION AND EXPERIMENTAL RESULTS
VI. CONCLUSION
REFERENCES
참고문헌 (17)
참고문헌 신청
J. Rodriguez, J. Lai, and F. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., Vol. 49, No. 4, pp.724-736, Aug. 2002.
Z. Pan, F. Peng, V. Stefanovic, and M. Leuthen, “A diode-clamped multilevel inverter with reduced number of clamping diodes,” IEEE Proc. of APEC’2004, pp. 820-824, 2004.
E. Babaei, S. Alilu, and S. Laali, “A new general topology for cascaded multilevel inverters with reduced number of components based on developed H-bridge,” IEEE Trans. Ind. Electron., Vol. 61, No. 8, pp. 3932-3939, Aug. 2014.
M. F. Kangarlu and E. Babaei, “A generalized cascaded multilevel inverter using series connection of sub-multilevel inverters,” IEEE Trans. Power Electron., Vol. 28, No. 2, pp. 625-636, Feb. 2013.
A. A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “Voltage sharing converter to supply single-phase asymmetrical four-level diode clamped inverter with high power factor loads,” IEEE Trans. Power Electron., Vol. 25, No. 10, pp. 2507-2520, Oct. 2010.
Z. Pan, F. Peng, V. Stefanovic, and M. Leuthen, “A diode-clamped multilevel inverter with reduced number of clamping diodes,” IEEE Proc. of APEC’2004, pp. 820-824, 2004.
E. Babaei, S. Alilu, and S. Laali, “A new general topology for cascaded multilevel inverters with reduced number of components based on developed H-bridge,” IEEE Trans. Ind. Electron., Vol. 61, No. 8, pp. 3932-3939, Aug. 2014.
M. F. Kangarlu and E. Babaei, “A generalized cascaded multilevel inverter using series connection of sub-multilevel inverters,” IEEE Trans. Power Electron., Vol. 28, No. 2, pp. 625-636, Feb. 2013.
A. A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “Voltage sharing converter to supply single-phase asymmetrical four-level diode clamped inverter with high power factor loads,” IEEE Trans. Power Electron., Vol. 25, No. 10, pp. 2507-2520, Oct. 2010.
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UCI(KEPA) : I410-ECN-0101-2016-560-002653918