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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2018.3
- 수록면
- 418 - 431 (14page)
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This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup.
목차
Abstract
I. INTRODUCTION
II. PROPOSED FUNDAMENTAL 11-LEVEL INVERTER
III. DC- LINK CAPACITOR VOLTAGE BALANCING AND RIPPLE VOLTAGE CALCULATION
IV. COMPARISON WITH OTHER RECENT TOPOLOGIES
V. SIMULATION AND EXPERIMENTAL RESULTS
VI. CONCLUSION
REFERENCES
참고문헌 (23)
참고문헌 신청
L. Maharjan, S. Inoue, H. Akagi, and J. Asakura. “State-ofcharge (SOC)-balancing control of a battery energy storage system based on a cascade PWM converter,” IEEE Trans. Power Electron, Vol. 24, No. 6, pp. 1628-1636, Jun. 2009.
K. Himour, K. Ghedamsi, and E. M. Berkouk, “Supervision and control of grid connected PV-Storage systems with the five level diode clamped inverter,” Energy Conversion and Management, Vol. 77, pp. 98-107, Oct. 2013.
M. F. Escalante, J.-.C. Vannier, and A. Arzande, “Flying capacitor multilevel inverters and DTC motor drive applications,” IEEE Trans. Ind. Electron, Vol. 49, No. 4, pp. 809-815, Aug. 2002.
K. Ramani, M. A. J. Sathik, and S. Sivakumar, “A new symmetric multilevel inverter topology using single and double source sub-multilevel inverters,” J. Power Electron., Vol. 15, No. 1, pp. 96-105, Jan. 2015.
A. Mokhberdoran and A. Ajami. “Symmetric and asymmetric design and implementation of new cascaded multilevel inverter topology,” IEEE Trans. Power Electron., Vol. 29, No. 2, pp. 6712-6724, Dec. 2014.
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