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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전기학회 Journal of Electrical Engineering & Technology Journal of Electrical Engineering & Technology Vol.12 No.2
- 발행연도
- 2017.3
- 수록면
- 701 - 710 (10page)
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초록· 키워드
오류제보하기
This paper presents a five-level PWM inverter using series and parallel connection of voltage sources. The alternative connection is done by an auxiliary circuit consisted of a switch, three diodes, and two batteries. The auxiliary circuit is located between input dc voltage source and H-bridge cell. Thanks to the auxiliary circuit, the proposed inverter synthesizes five-level output voltage in an effective way. Topologically both batteries are charged and discharged in the same rate, so it does not need to apply battery voltage balancing control method. Theoretical analysis of the proposed inverter is verified by computer-aided simulation and experiment based on a prototype of 1kW.
목차
Abstract
1. Introduction
2. Proposed Five-level PWM Inverter
3. Simulations and Experiment Results
4. Conclusion
References
참고문헌 (24)
참고문헌 신청
K. K. Gupta and S. Jain, “Comprehensive review of a recently proposed multilevel inverter,” IET Power Electron., vol. 7, no. 3, pp. 467-479, 2014.
M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, “A Survey on Cascaded Multilevel Inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2197-2206, July 2010.
Rodrigues J, Lai J. S, and Peng F. Z, “Multilevel inverters : A survey of topologies, controls and application,” IEEE Trans. on Ind. Electron., vol. 49, no. 4, pp. 724-738, 2002.
E. Najafi and A. H. M. Yatim, “Design and Implementation of a New Multilevel Inverter Topology,” IEEE Trans. Ind. Electron., vol. 59, no. 11, pp. 4148- 4154, 2012.
J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A New Multilevel Converter Topology With Reduced Number of Power Electronic Components,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 655-667, 2012.
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