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자료유형
학술저널
저자정보
Nho-Van Nguyen (Ho Chi Minh City University of Technology) Tam-Khanh Tu Nguyen (Ho Chi Minh City University of Technology)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.19 No.4
발행연도
2019.7
수록면
907 - 921 (15page)

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This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.

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Abstract
I. INTRODUCTION
II. GENERALIZED ZCMV PWM SEQUENCES FOR MULTILEVEL INVERTERS
III. PROPOSED PWM ALGORITHMS FOR REDUCED OUTPUT-CURRENT RIPPLE IN MULTILEVEL INVERTERS
IV. HARMONIC DISTORTION FACTOR
V. DEAD-TIME EFFECT ANALYSIS
VI. SIMULATION AND EXPERIMENTAL RESULTS
VII. CONCLUSION
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UCI(KEPA) : I410-ECN-0101-2019-560-000866975