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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.6
- 발행연도
- 2022.12
- 수록면
- 482 - 492 (11page)
- DOI
- 10.5573/JSTS.2022.22.6.482
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초록· 키워드
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This paper compares four phase-locked loops (PLLs) for mobile audio applications. We compare and analyze PLL structures and discuss the optimized PLL structure in the audio band frequency. A charge-pump-based integer-N PLL (NPLL) is employed as a reference. To improve the jitter performances, multiplying delay-locked loop (MDLL), sub-sampling PLL (SSPLL), and reference-sampling PLL (RSPLL) are employed and analyzed. The frequency range of the PLLs is from 8 MHz to 71.5 MHz. These PLL chips are fabricated using a Samsung 0.13-μm CMOS process. The resulting figures-of-merit for the NPLL, MDLL, SSPLL, and RSPLL are -204.3, -211.07, -220.29, and -213.32 dB, respectively, at 24.576 MHz. The total power consumption from a 1.5-V supply voltage is 1.82, 1.35, 1.43, and 1.64 mW, respectively.
목차
Abstract
I. INTRODUCTION
II. PLL CONFIGURATIONS FOR AUDIO SYSTEMS
III. CIRCUIT DESCRIPTION
IV. PHASE NOISE ANALYSIS
V. MEASUREMENT RESULTS
VI. CONCLUSIONS
REFERENCES
참고문헌 (18)
참고문헌 신청
Inter-IC Sound Bus (I2S) 2.70 component datasheet, Infineon, Neubiberg, Germany, 2015.
J. A. Crawford, Frequency Synthesizer Design Handbook. Boston, MA: Artech House, 1994.
Santiccioli, Alessio, et al. "A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power." IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3149-3160, Nov. 2019.
Santiccioli, Alessio, et al. "A 66-fs-rms jitter 12.8-to-15.2-GHz fractional-N bang-bang PLL with digital frequency-error recovery for fast locking." IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3349-3361, Dec. 2020.
Zhang, Zhao, Guang Zhu, and C. Patrick Yue. "A 0.65-V 12-16-GHz sub-sampling PLL with 56.4-fs rms integrated jitter and− 256.4-dB FoM." IEEE Journal of Solid-State Circuits, vol. 55, no. 6, pp. 1665-1683, Jun. 2020.
J. A. Crawford, Frequency Synthesizer Design Handbook. Boston, MA: Artech House, 1994.
Santiccioli, Alessio, et al. "A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power." IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3149-3160, Nov. 2019.
Santiccioli, Alessio, et al. "A 66-fs-rms jitter 12.8-to-15.2-GHz fractional-N bang-bang PLL with digital frequency-error recovery for fast locking." IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3349-3361, Dec. 2020.
Zhang, Zhao, Guang Zhu, and C. Patrick Yue. "A 0.65-V 12-16-GHz sub-sampling PLL with 56.4-fs rms integrated jitter and− 256.4-dB FoM." IEEE Journal of Solid-State Circuits, vol. 55, no. 6, pp. 1665-1683, Jun. 2020.
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