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논문 기본 정보

자료유형
학술저널
저자정보
Kai Li (University of Electronic Science and Technology of China) An Bo (University of Electronic Science and Technology of China) Hong Zheng (University of Electronic Science and Technology of China) Ningbo Sun (Jinan Huizhi Electric Power Technology)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.17 No.1
발행연도
2017.1
수록면
262 - 271 (10page)

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초록· 키워드

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This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

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Abstract
I. INTRODUCTION
II. THREE-PHASE PHASE-LOCK LOOP SYNCHRONIZATION TECHNIQUE
III. PARAMETER DESIGN AND ANALYSIS
IV. SIMULATION AND EXPERIMENTAL RESULTS
V. CONCLUSIONS
REFERENCES

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UCI(KEPA) : I410-ECN-0101-2017-560-002047870