A Study on DCPLL with Low Jitter

Kuniaki FUJIMOTO ,  Mitsuthosi YAHARA ,  Hi 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2004 .07

Tracking analog - to - digital 변환기를 이용한 digital phase - locked loop

차수호 ,  유창식

전자공학회논문지-SD

2005 .09

Automatic Clock Jitter Analysis Considering Clock Divider

Woojin Jin ,  Moon-su Kim ,  Chan-min Jo 외 2명

대한전자공학회 ISOCC

2009 .11

Low jitter 1.5㎓ spread spectrum clock generator

Chang Su Sim ,  Chung Hwan Son ,  Sangjin Byun

대한전자공학회 ISOCC

2012 .11

IP 망에서의 네트워크 지터 모델에 관한 연구

신상헌 ,  구수용

대한전자공학회 학술대회

2014 .11

A low jitter spread spectrum clock generator using 3㎓ LC oscillator

Jongil Hwang ,  Chung Hwan Son ,  Sangjin Byun

대한전자공학회 ISOCC

2012 .11

동기망에서의 Recovered Clock Jitter와 Bit Leaking 기술

최선학

전자공학회지

1993 .04

Performance Analysis of Track Loops with Jitter of System Clock in UWB-IR Systems

Juyeon Jeong ,  Jichai Jeong

한국통신학회 학술대회논문집

2005 .11

Low Power Clock Distribution

조경록

대한전자공학회 학술대회

1997 .01

Jitter Reduction on Clock Distribution Path using Chip-Package Hybrid Interconnection

Daehyun Chung ,  Chunghyun Ryu

대한전자공학회 ISOCC

2004 .10

안전한 MCU 클럭 보호를 위한 온칩 클럭 검사기 기반 자동화된 글리치 프리 백업 클럭 변환 기법

안중현 ,  박대진 ,  조정훈

대한전자공학회 학술대회

2015 .06

Computer Simulation of Jitter Characteristics of PLL for Arbitrary Data and Jitter Patterns

Kenichi Nakashi ,  Hi ,  oyuki Shi 외 6명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1993 .01

A 0.12㎓-1.4㎓ DLL-based Clock Generator with a Multiplied 4-phase Clock Using a 0.18㎛ CMOS Process

Hyung-Joon Chi ,  Jae-seung Lee ,  Jae-Yoon Sim 외 2명

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2006 .12

Delay-Locked Loop를 이용한 고속 클럭 임베디드 Interface에서의 Low Jitter 전하펌프

박상현 ,  김석기

대한전자공학회 학술대회

2013 .11

Design of Clock Gears for Low-power Media Bus

Yong-Hwan Lee ,  Hoon-Ju Chung ,  Chang-Gu Rho

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2008 .07

불규칙 Pulse 신호의 전력 Spectrum ( Power Spectrum of Jittered Random Pulse Train )

최양희 ,  김재균

전자공학회지

1980 .02

A low jitter Spread Spectrum Clock Generator using Varactor delay line

Gautam Kuma ,  Singh

대한전자공학회 ISOCC

2013 .11

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

Hyunbean Yi

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2013 .02

Design Methodologies for Reliable Clock Networks

Deokjin Joo ,  Minseok Kang ,  Taewhan Kim

Journal of Computing Science and Engineering

2012 .12

Design of 2.5Gb/s non-PLL-type All-Digital Clock Recovery Circuit

Soojin Kim ,  Kyeongsoon Cho

대한전자공학회 ISOCC

2010 .11