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논문 기본 정보

자료유형
학술저널
저자정보
Soundar Rajan Ponnusamy (PSNA College of Engineering & Technology) Manoharan Subramaniam (PSNA College of Engineering & Technology) Gerald Christopher Raj Irudayaraj (Karpagam College of Engineering) Kaliamoorthy Mylsamy (Dr. Mahalingam College of Engineering & Technology)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.17 No.1
발행연도
2017.1
수록면
115 - 126 (12page)

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초록· 키워드

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This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.

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Abstract
I. INTRODUCTION
II. PROPOSED CIRCUIT TOPOLOGY
III. BALANCING CAPACITOR VOLTAGE USING A MULTILEVEL INVERTER
IV. SIMULATION RESULTS
V. EXPERIMENTAL RESULTS
VI. CONCLUSIONS
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UCI(KEPA) : I410-ECN-0101-2017-560-002047734