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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2019.6
- 수록면
- 97 - 100 (4page)
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초록· 키워드
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Because nanoelectromechanical (NEM) memory switches have higher pull-in voltage (V<SUB>PI</SUB>) and lower reliability than CMOS devices, reducing V<SUB>PI</SUB> and maximum stress (σ<SUB>MAX</SUB>) of NEM memory switches are critical issues of implementing monolithic-3D (M3D) CMOS-NEM hybrid reconfigurable logic (RL) circuits. In this paper, we propose a novel notched anchor design to reduce the V<SUB>PI</SUB> and σ<SUB>MAX</SUB> of NEM memory switches. In the case of the proposed NEM memory switches, their anchors are placed in the vias of metal interconnection layers. Thus, if notched patterns are patterned onto the anchors, it will be helpful to effectively increase beam length, which eventually lowers V<SUB>PI</SUB> and σ<SUB>MAX</SUB> while boosting chip density. In this manuscript, our proposed idea has been confirmed by finite-element-method (FEM) simulation. According to the simulation results, the proposed notched anchor design lowers V<SUB>PI</SUB> by ~23 % and σ<SUB>MAX</SUB> by ~24 %.
목차
Abstract
I. Introduction
II. Results and discussion
III. Conclusion
References
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