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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.5
- 발행연도
- 2019.10
- 수록면
- 505 - 509 (5page)
- DOI
- 10.5573/JSTS.2019.19.5.505
이용수
초록· 키워드
오류제보하기
A novel low voltage and low power truesingle-phase flip-flop (FF) design is proposed in this paper. It is adapted from conventional Set-Reset latch based FF design and achieves circuit simplification by using virtual VDD scheme. The optimization measure leads to a new design providing better various performances. Based on post layout simulation results using the TSMC CMOS 180 ㎚ technology, the proposed design outperforms the conventional TGFF by 68.7% in energy consumption (at 25% switching activity).
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED DESIGN
Ⅲ. SIMULATION RESULTS
Ⅵ. CONCLUSIONS
REFERENCES
참고문헌 (9)
참고문헌 신청
H. Kawaguchi and T. Sakurai, “A reduced clockswing flip-flop (RCSFF) for 63% power reduction,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807?811, May 1998.
V. Stojanovic and V. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536?548, Apr. 1999.
B. Kong, S. Kim, and Y. Jun, “Conditional-capture flip-flop for statistical power reduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263?1271, Aug. 2001.
E. Consoli, M. Alioto, G. Palumbo, J. Rabaey, “Conditional push-pull pulsed latch with 726 fJ?ps energy delay product in 65nm CMOS,” in Proc. IEEE Dig. ISSCC, 2012, pp. 482-483.
Chen, K., et al.: ‘A 77% energy saving 22- transistor single phase clocking D-flip-flop with adoptive-coupling configuration in 40nm CMOS’, ISSCC Dig. Tech. Papers, Feb. 2011, pp. 338-339.
V. Stojanovic and V. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536?548, Apr. 1999.
B. Kong, S. Kim, and Y. Jun, “Conditional-capture flip-flop for statistical power reduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263?1271, Aug. 2001.
E. Consoli, M. Alioto, G. Palumbo, J. Rabaey, “Conditional push-pull pulsed latch with 726 fJ?ps energy delay product in 65nm CMOS,” in Proc. IEEE Dig. ISSCC, 2012, pp. 482-483.
Chen, K., et al.: ‘A 77% energy saving 22- transistor single phase clocking D-flip-flop with adoptive-coupling configuration in 40nm CMOS’, ISSCC Dig. Tech. Papers, Feb. 2011, pp. 338-339.
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