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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.6
- 발행연도
- 2017.12
- 수록면
- 862 - 877 (16page)
- DOI
- 10.5573/JSTS.2017.17.6.862
이용수
초록· 키워드
오류제보하기
Most of static timing analyses today are based on conventional fixed flip-flop timing models, in which every flip-flop is assumed to have a fixed clock-to-Q delay. However, since the setup and hold skews affect the clock-to-Q delay in reality, many researchers have paid attention to the flexible flip-flop timing property in circuit timing analysis and optimization. Nevertheless, the existing works have failed in solving the problem of exactly formulating the sequences of timing dependency among the skews and delays over time. In this work, we solve the problem, specifically, (1) proposing a mathematical formulation to solve the problem, (2) applying our solution to the analysis of a given circuit as well as (3) to the clock skew scheduling problems, and (4) proposing a speedup technique. Through experiments with benchmark circuits, it is demonstrated that our method can rectify improper or unoptimized results drawn from the previous approach. It is also shown that our speedup technique is able to shorten run times significantly with very little loss of optimality.
목차
Abstract
I. INTRODUCTION
II. PRELIMINARIES
III. CLOCK-TO-Q DELAY INTERVAL ANALYSIS
IV. APPLICATIONS OF CLOCK-TO-Q DELAY INTERVAL ANALYSIS UNDER FLEXIBLE FLIP-FLOP TIMING MODEL
V. EXPERIMENTAL RESULTS
V. CONCLUSION
REFERENCES
참고문헌 (26)
참고문헌 신청
J. Heo and T. Kim, “Timing analysis and optimization based on flexible flip-flop timing model,” VLSI, IEEE Computer Society Annual Symposium on, pp. 42-46, Jul., 2016.
“Nangate open cell library,” http://www.nangate. com, 2009.
V. Stojanovic and V. G. Oklobdzija, “Comparative analysis of master slave latches and flip-flops for high-performance and low-power systmes,” Solid- State Circuits, IEEE Journal of, Vol. 34, No. 4, pp. 536-548, Apr., 1999.
A. M. Jain and D. Blaauw, “Modeling flip flop delay dependencies in timing analysis,” ACM Timing Issues (TAU) Workshops, pp. 67-73, Feb., 2004.
G. Rao and K. Howick, “Apparatus for optimized constraint characterization with degradation options and associated methods,” U. S. Patent No. 6,584,598, Jun., 2003.
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UCI(KEPA) : I410-ECN-0101-2018-569-001738008