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논문 기본 정보

자료유형
학술저널
저자정보
Gurpurneet Kaur (I. K. Gujral Punjab Technical University) Sandeep Singh Gill (National Institute of Technical Teachers Training and Research) Munish Rattan (Guru Nanak Dev Engineering College)
저널정보
한국전기전자재료학회 Transactions on Electrical and Electronic Materials Transactions on Electrical and Electronic Materials 제22권 제6호
발행연도
2021.12
수록면
774 - 785 (12page)
DOI
https://doi.org/10.1007/s42341-021-00296-2

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Inherent variations and the challenge of leakage current control in today’s silicon-on-insulator metal?oxide?semiconductor field-effect transistor limits the scaling of static random-access memory. The fin-shaped field-effect transistor has been considered an attractive device for designing low power SRAM cells. In this work, a 14 nm gate length FinFET device has been designed with lanthanum doped zirconium oxide as a compound gate dielectric material. The diminished subthreshold swing (60 mV/dec), reduced leakage current (10 ?14 ), lowered drain induced barrier lowering (10.6 mV/V), enhanced drive current (3.74 × 10 ?5 ), and increased g m (2.27 × 10 ?4 ) were observed after simulating this optimized device. Further, two SRAM cells based on the improved device were implemented with different fin configurations. The stability parameters were investigated with the butterfly curve method. The SRAM Cell-I has presented better read static noise margin and write static noise margin in comparison to the SRAM Cell-II. The impact of supply voltage variations on stability metrics and leakage power has also been presented.

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