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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.25 No.2
- 발행연도
- 2025.4
- 수록면
- 166 - 175 (10page)
- DOI
- 10.5573/JSTS.2025.25.2.166
이용수
초록· 키워드
오류제보하기
In pulse amplitude modulation 4-level (PAM-4) receiver design, the variation of the effective least significant bit (LSB) threshold voltage degrades the margin of LSB decision and worsens the bit error rate (BER). This paper proposes a dynamic comparator to solve the problem. The proposed dynamic comparator features low variability in effective LSB threshold voltage due to its common-mode-rejection capability. The proposed dynamic comparator has been designed and simulated at post-layout level in a 45 nm CMOS with 1.1 V supply voltage. The effective LSB threshold voltage variations of the conventional and proposed dynamic comparators are quantitatively analyzed and compared by simulation results.
목차
Abstract
I. INTRODUCTION
II. EFFECTIVE LSB THRESHOLD VOLTAGE
III. CONVENTIONAL DYNAMIC COMPARATORS
IV. PROPOSED REFERENCELESS DYNAMIC COMPARATOR
V. SIMULATION RESULTS
VI. CONCLUSIONS
REFERENCES
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