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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.15 No.2
- 발행연도
- 2015.4
- 수록면
- 168 - 176 (9page)
이용수
초록· 키워드
오류제보하기
Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS’89 benchmark circuits show that our method is more accurate and efficient than previous methods.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. RELATED WORK
Ⅲ. SUSCEPTIBILITY ANALYSIS FOR SEQUENTIAL CIRCUIT ELEMENTS
Ⅳ. EXPERIMENTAL RESULTS
5. CONCLUSIONS
REFERENCES
참고문헌 (16)
참고문헌 신청
1. [학술지(정기간행물)] - J. F. Ziegler / 1996 / IBM experiments in soft fails in computer electronics (1978 – 1994) / IBM Journal of Research and Development 40 (1) : 3 ~ 18
2. [학술지(정기간행물)] - D. T. Franco / 2006 / Yield and reliability issues in nanotechnologies / Annales des telecommunications 61 (11-12) : 1422 ~ 1457
3. [학술대회논문] - P. Shivakumar / 2002 / Modeling the effect of technology trends on the soft error rate of combinatorial logic / Proc. Int’l Conf. on Dependable Systems and Networks(DSN) : 389 ~ 398
4. [학술대회논문] - H. Asadi / 2005 / Soft error modeling and protection for sequential elements / Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst : 463 ~ 471
5. [학술대회논문] - K. Mohanram / 2003 / Cost-effective approach for reducing soft error failure rate in logic circuits / Test Conference, 2003. Proceedings. ITC 2003. International 1 : 893 ~ 901
2. [학술지(정기간행물)] - D. T. Franco / 2006 / Yield and reliability issues in nanotechnologies / Annales des telecommunications 61 (11-12) : 1422 ~ 1457
3. [학술대회논문] - P. Shivakumar / 2002 / Modeling the effect of technology trends on the soft error rate of combinatorial logic / Proc. Int’l Conf. on Dependable Systems and Networks(DSN) : 389 ~ 398
4. [학술대회논문] - H. Asadi / 2005 / Soft error modeling and protection for sequential elements / Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst : 463 ~ 471
5. [학술대회논문] - K. Mohanram / 2003 / Cost-effective approach for reducing soft error failure rate in logic circuits / Test Conference, 2003. Proceedings. ITC 2003. International 1 : 893 ~ 901
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UCI(KEPA) : I410-ECN-0101-2016-569-001461739