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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2022.6
- 수록면
- 198 - 201 (4page)
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초록· 키워드
오류제보하기
To optimize low power hardware for memory-centric computing such as processing-in-memory (PIM) and hardware neural network (HNN), a gated diode with charge storage has been proposed. The key is that considering the parallel computing performed in memory, reducing operation current and increasing on/off ratio are essential.
In this study, the current mechanism of fabricated bulk gated diode has been analyzed and a device structure has been proposed to reduce leakage current. By classifying the current mechanism according to the device physics and analyzing it with considering device design, the leakage current can be reduced by adopting an optimized SOI structure. In addition, it was confirmed that in a fabricated SOI gated diode, the leakage current was approximately two orders of magnitude smaller than that in bulk gated diode.
In this study, the current mechanism of fabricated bulk gated diode has been analyzed and a device structure has been proposed to reduce leakage current. By classifying the current mechanism according to the device physics and analyzing it with considering device design, the leakage current can be reduced by adopting an optimized SOI structure. In addition, it was confirmed that in a fabricated SOI gated diode, the leakage current was approximately two orders of magnitude smaller than that in bulk gated diode.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Result and Discussion
Ⅳ. Conclusion
References
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