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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2009.11
- 수록면
- 224 - 227 (4page)
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초록· 키워드
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It is common that high performance integrated circuit today achieves faster processing speed by padding as many memory cells or SRAM (Static Random Access memory) in its core logic as possible [1]. The build-in SRAM cell allows the PCH (Platform Controller Hub) to access the nearest data storage with least latency. While the SRAM cells are aggressively populating the PCH core, the total chip power consumption is increasing. Power gating technology becomes a juicy implementation on these SRAM to turn off the power when it is not in used. In this project, the computing power savings have achieved ~900mW and proven to be a good strategy for preserving mobile computing power and extension of battery life span. However, the aggressive implementation of power gating and un-gating technology, if not understood fully, will be leading to uncontrollable transient ac noise on the power delivery network (PDN) and ultimately impacting the PCH core performance.
This paper describes a comprehensive approach in characterizing and optimizing the PDN invoked by the multiple SRAM cells power gate/un-gate dynamically. By deriving the worst case possible configurations on which each power gate/ un-gate could happen within the same power supply domain, it allows the designer to first guesstimate how severe each transient droop will occur. This is followed by customizing the SRAM cells using a configurable clock latency to offset the power un-gate timing and spreading out the SSO (simultaneous switching output) noise such that the voltage droop is contained within an allowable budget. Secondary effect such as the sudden lost of capacitance reservoir following the power gate of SRAM and the appropriate approach in quantifying the SRAM capacitance during power gated and un-gated is discussed in this paper too.
The paper is concluded with post-silicon measurement of SRAM power gate/un-gate transient characterization behavior, showing a good correlation to within 96% match to the pre-silicon estimate. It is a proven method and can be leveraged to many processor and chipset designs which are looking for aggressive power savings while preserving the core performance to its optimum.
This paper describes a comprehensive approach in characterizing and optimizing the PDN invoked by the multiple SRAM cells power gate/un-gate dynamically. By deriving the worst case possible configurations on which each power gate/ un-gate could happen within the same power supply domain, it allows the designer to first guesstimate how severe each transient droop will occur. This is followed by customizing the SRAM cells using a configurable clock latency to offset the power un-gate timing and spreading out the SSO (simultaneous switching output) noise such that the voltage droop is contained within an allowable budget. Secondary effect such as the sudden lost of capacitance reservoir following the power gate of SRAM and the appropriate approach in quantifying the SRAM capacitance during power gated and un-gated is discussed in this paper too.
The paper is concluded with post-silicon measurement of SRAM power gate/un-gate transient characterization behavior, showing a good correlation to within 96% match to the pre-silicon estimate. It is a proven method and can be leveraged to many processor and chipset designs which are looking for aggressive power savings while preserving the core performance to its optimum.
목차
Abstract
1. Introduction
2. Construction of worst case SRAM current load
3. Characterization of PDN Z(f)
5. Pre v.s. Post Silicon Correlation
6. Summary and Conclusion
7. References
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