지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2010.11
- 수록면
- 5 - 8 (4page)
이용수
초록· 키워드
오류제보하기
A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by up to 3.84x and the read static noise margin is increased by up to 4.79x with the new memory power gating technique as compared to a previously published power gated 6T SRAM circuit in a UMC 80nm CMOS technology.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. OLD POWER GATED 6T SRAM CIRCUIT
Ⅲ. A NOVEL POWER GATED 6T SRAM CIRCUIT
Ⅳ. CHARACTERIZATION OF SRAM CIRCUIT TECHNIQUES
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
A Low-leakage SRAM using Power-gating and Virtual-ground
대한전자공학회 ISOCC
2012 .11
-
SRAM Core Modeling Methodology for Efficient Power Delivery Analysis
대한전자공학회 ISOCC
2009 .11
-
Data Stability Enhancement Techniques for Nanoscale Memory Circuits : 7T Memory Design Tradeoffs and Options in 80nm UMC CMOS Technology
대한전자공학회 ISOCC
2010 .11
-
FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability
Transactions on Electrical and Electronic Materials
2015 .01
-
A Novel Leakage Power Reduction Technique for CMOS Circuit Design
대한전자공학회 ISOCC
2010 .11
-
Novel High Electrical Quality Seven-Transistor Memory Cell with Asymmetrical Ground Gating
대한전자공학회 ISOCC
2013 .11
-
Self-Power Gating Technique For Low Power Asynchronous Circuit
전기전자학회논문지
2018 .09
-
파워게이팅과 전압레벨조절을 이용하여 누설전류를 줄인 SRAM
전자공학회논문지-SD
2012 .08
-
An Advanced Embedded SRAM Cell with Expanded Read/Write Stability and Leakage Reduction
전기전자학회논문지
2012 .09
-
Stability Enhancement Techniques for Nanoscale SRAM Circuits : A Comparison
대한전자공학회 ISOCC
2008 .11
-
누설전류억제 SRAM을 위한 Power Gating 회로 연구
대한전자공학회 학술대회
2006 .11
-
Performance and Wake-Up Schedule Optimization of Power Gating Design
대한전자공학회 ISOCC
2008 .11
-
SOC Power Off – Power Noise Analysis
대한전자공학회 ISOCC
2009 .11
-
Multi-valued SRAM cell with FG-MOSFETs
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2007 .07
-
Sleep transistor sizing through a path search and power gating considering delay for reducing leakage power
ICEIC : International Conference on Electronics, Informations and Communications
2010 .06
-
Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2014 .04
-
A Gate Modification Method Using the Input Vector Maximizes the Number of Gates in WLS within the Optimum Range
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2007 .07
-
65-㎚급 SoC를 위한 증가된 Word-Line-Off 전압을 이용한 Oxide-Tunneling 누설전류 절감 SRAM
대한전자공학회 학술대회
2008 .05
-
Introduction to Industrial Applications of Low Power Design Methodologies
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2009 .12
-
초미세 CMOS 공정에서의 스위칭 및 누설전력 억제 SRAM 설계
전자공학회논문지-SD
2006 .03
이 논문의 저자 정보
이 논문과 함께 이용한 논문
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2013-569-001488798